1. Field of the Invention
The present invention relates to a power semiconductor device and a method of manufacturing the same, and especially to a technique for reducing photolithography process steps and preventing a decrease in breakdown voltage due to the reduction of the process steps.
2. Description of the Background Art
A conventional power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is manufactured as follows.
First, an n−-type silicon layer is grown epitaxially on an n+-type silicon substrate. A silicon oxide film (hereinafter also referred to as an “oxide film”) is then formed on a main surface of the above epitaxial layer. A photoresist pattern is formed on the oxide film using photolithography techniques and using the photoresist pattern as a mask, a portion of the oxide film which is located within a central region of an element configuration part is etched to form an opening. At this time, a portion of the epitaxial layer which is located within an outer peripheral region (peripheral region) of the element configuration part is covered (masked) with the remaining oxide film. Then, using the photoresist pattern and the open oxide film as masks, p-type impurities (such as boron) are ion implanted and then heat treatment is carried out, thereby to form a p base layer of the power MOSFET in the main surface of the epitaxial layer. Thereafter, the photoresist pattern is removed.
Then, a photoresist pattern having an opening within the central region is formed using photolithography techniques. At this times, the opening of the photoresist pattern is formed narrower than that of the above oxide film, so that not only the oxide film but also a portion of the p base layer in the vicinity of the opening of the oxide film are covered with the photoresist pattern. Using the photoresist pattern as a mask, n-type impurities (such as arsenic) are ion implanted and then heat treatment is carried out, thereby to form an n+ source layer of the power MOSFET in the main surface of the p base layer. Thereafter, the photoresist pattern is removed.
Then, an insulating film is formed across the surface by CVD (Chemical Vapor Deposition) to cover the above oxide film and the exposed main surface in the opening of the oxide film. Subsequently, a photoresist pattern having an opening corresponding to a gate trench is formed on the insulating film by using photolithography techniques and the above insulating film is etched using the photoresist pattern as a mask. After removal of the photoresist pattern, using the patterned insulating film as a mask, the n+ source layer, the p base layer and the epitaxial layer are etched to form a gate trench. Thereafter, the insulating film used as a mask is removed and a gate oxide film is formed on the exposed surface.
Then, n-type polysilicon is deposited by CVD to fill in the gate trench and to extend to a level above the main surface. The polysilicon is then etched back to a predetermined thickness. A photoresist pattern is formed using photolithography techniques to cover a portion of the polysilicon which is extended out of the trench onto the oxide film. Thereafter, using the photoresist pattern as a mask, the polysilicon is dry etched to the same level as the main surface or to a level therebelow. This forms a gate polysilicon electrode. For normal operation of the MOS transistor, the upper surface of the polysilicon in the trench should be located at a higher level than a junction face between the p base layer and the n+ source layer. Thereafter, the photoresist pattern is removed.
A cap oxide film is formed on the exposed surface of the polysilicon, and borophoshposilicate glass (BPSG) as an interlayer insulation film is further deposited by CVD.
Then, a photoresist pattern having openings for source and gate contact holes is formed on the interlayer insulation film by using photolithography techniques. Using the photoresist pattern as a mask, the interlayer insulation film and the like are etched to form source and gate contact holes. Thereafter, the photoresist pattern is removed. The source contact hole is formed to extend through the n+ source layer to the p base layer in the vicinity of the gate polysilicon electrode. The gate contact hole is formed on the oxide film within the outer peripheral region to expose therein a portion of the gate polysilicon electrode which is extended out of the gate trench.
Then, a conductive Al—Si film is deposited across the surface by sputtering so as to fill in the source and gate contact holes and a photoresist pattern is formed on the Al—Si film by using photolithography techniques. Using the photoresist pattern as a mask, etching is performed to form a source aluminum electrode and a gate aluminum electrode of the Al—Si film. The photoresist pattern is then removed.
Thereafter, a conductive Ti—Ni—Au alloy is deposited by sputtering on the entire surface of the substrate on the side opposite the epitaxial layer, thereby to form a drain electrode.
Through the aforementioned process steps, a conventional power MOSFET is completed.
Now, the breakdown voltage of the aforementioned conventional power MOSFET is described. Under conditions where the source aluminum electrode is placed at a ground potential and the drain electrode is placed at a positive potential, a depletion layer is generated at the junction between the p base layer and the epitaxial layer. Since the depletion layer generally spreads in proportion to the ½-th power of the applied voltage, current also increases in proportion to the ½-th power of the voltage. If the strength of an electric field applied to the depletion layer exceeds a certain value with increased voltage, an avalanche breakdown occurs. Usually, in order to prevent the occurrence of an avalanche breakdown, a voltage equivalent to about 80% of the avalanche breakdown voltage is employed. At this time, since the outer end of the p base layer has a curvature, the electric field applied to the depletion layer is further increased and the breakdown voltage becomes smaller than a one-dimensional pn junction breakdown voltage. Thus, several structures are suggested for improving the breakdown voltage of a power device having a curvature. Examples of typical structures include a field ring (or guard ring) structure and a field plate structure which are widely and commonly used. In the field ring structure, by forming a p-type layer being in a multiple floating state in the outer periphery of the p base layer which forms a main junction, the curvature is reduced and the depletion layer is kept uniform. In the field plate structure, an electrode is located directly above and outside the p base layer through an insulating film and a negative voltage is applied to that electrode, which allows easy outward spread of the depletion layer and reduction of the curvature.
The aforementioned conventional manufacturing method is introduced in, for example, International Publication No. 99/12214.
The aforementioned conventional power MOSFET manufacturing method utilizes photolithography techniques in the following six process steps: (1) the step of forming the p base layer; (2) the step of forming the n+ source layer; (3) the step of forming the gate trench; (4) the step of patterning the gate polysilicon electrode; (5) the step of forming the contact holes; and (6) the step of patterning the aluminum electrode.
If the photolithography process step that is used in forming the n+ source layer is eliminated for reduction of manufacturing process steps, the following problem arises. That is, ion implantation for formation of the n+ source layer must be performed in a self-aligned manner, using as a mask, again the oxide film which was used in ion implantation for formation of the p base layer (double diffusion techniques). In this case, the outer end of the n+ source layer is located closer to the outer end of the p base layer than when using the previously described mask for formation of the n+ source layer (i.e., a photoresist pattern having an opening narrower than that of the oxide film). That is, the p base layer has a narrower width in its outer peripheral portion; in other words, a distance between the outer peripheries of the p base layer and the n+ source layer is reduced. This can easily cause punch-through, thereby decreasing the breakdown voltage.